FIG. 1 shows a time-continuous sigma/delta analog-to-digital converter according to the prior art. The conventional sigma/delta analog-to-digital converter firstly converts an analog input signal in a sigma/delta pulse density modulator into a high-frequency serial bit sequence normally having single bit resolution, that is to say into a high-frequency coarsely quantized sample value. The modulator output signal is converted into highly resolving parallel words, which have a substantially lower sampling rate, by subsequent digital low pass filtering. The energy of the quantization noise is distributed uniformly over a wide frequency band by the oversampling.
A sigma/delta analog-to-digital converter (ΣΔADC) comprises two main constituents, specifically a delta/sigma modulator and a digital filter. Firstly, an analog-to-digital conversion of low resolution, for example single bit resolution, is executed, and the quantization noise is subsequently greatly reduced by digital filtering.
The sigma/delta modulator according to the prior art as illustrated in FIG. 1 has a feedback loop which comprises a subtractor, an integrator, a coarse quantizer or comparator and a digital-to-analog converter in the feedback branch. The quantizer comprises an analog-to-digital converter (ADC) of low resolution but with a high sampling rate, which supplies a digital output signal. The digital-to-analog converter (DAC) provided in the feedback branch generates from the digital output signal sequence a quantized analog signal or approximation signal that is subtracted at the subtractor from the analog input signal. In an implementation that is simple in terms of circuitry, the digitization or quantization is performed merely with single bit resolution, the quantizer being implemented by a simple Schmitt trigger or analog comparator. The approximation signal is compared with the analog input signal in the feedback loop, and the difference is fed in an integrated fashion to the quantizer. The control loop corrects the arithmetic mean value of the approximation voltage to the mean value of the input voltage.
FIG. 2 shows a sigma/delta modulator according to the prior art that is of simple design in terms of circuitry. The integrator is implemented in this case by an operational amplifier whose output is fed back via a capacitor to the inverting signal input of the operational amplifier. The output of the integration amplifier specifies the integrated signal at the input of a threshold comparator which supplies a digital output signal of single bit resolution. The digital output signal is fed back via an inverter and via a resistor R to a summing node which is connected to the inverting input of the operational amplifier.
The main difficulty in implementing sigma/delta analog-to-digital converters is generating the analog feedback signal fed back to the integrator. The analog feedback signal output by the digital-to-analog converter DAC should map the digital output signal as exactly as possible. In the case of a conventional sigma/delta modulator according to the prior art, as illustrated in FIGS. 1 and 2, a logically high data bit of the digital output signal (HIGH) is applied as a first reference voltage (for example VREF1=1 volt) to the inverting signal input of the operational amplifier, and a logically low signal (low) of the digital signal is fed back as a second reference voltage (for example VREF2=0 volt) to the inverting signal input of the operational amplifier.
FIG. 3 shows two approximation signals fed back to the signal input of the integrator I and which correspond to different bit sequences of the output signal. The first data bit sequence “0 1 0 1” and the second data bit sequence “0 1 1 0” are fed back in the case of the feedback signals illustrated in FIG. 3 as NRZ (Non Return to Zero) data signals to the integrator I. As may be seen from comparing FIGS. 3a and 3b, the voltage integral of the two feedback signals, which corresponds to the charge Q fed to the integrator I or drawn from the integrator I, differs for the two different data bit sequences, although they ideally have to be equal in order to ensure complete linearity of the analog-to-digital converter ADC. In order to raise the linearity, the approximation signal is therefore fed back as RZ (Return to Zero) signal, as illustrated in FIGS. 4a, 4b. As may be seen from FIGS. 4a, 4b, the voltage integral, which corresponds to the charge Q displaced to/from the integrator I, is the same for both data bit sequences, and so the linearity of the analog-to-digital converter is greatly improved by comparison with the fed back approximation signals illustrated in FIGS. 3a, 3b. 
The disadvantage in the case of the approximation signals illustrated in FIGS. 4a, 4b is, however, that they are particularly sensitive to clock jitter of the clock signal (CLK). The reason for this is that in the case of the RZ approximation signals in accordance with FIG. 4, the signal pulse length is reduced by comparison with the NRZ approximation signals which are illustrated in FIGS. 3a, 3b, and so a clock jitter of the signal edges has a stronger effect on the displaced charge Q or the voltage integral. In order to reduce the sensitivity of time-continuous sigma/delta analog-to-digital converters with respect to clock jitter, use is therefore made of more strongly switched capacitors in the feedback branch of the sigma/delta modulator, as illustrated in FIG. 5. A switch S is driven by the clock signal CLK, and alternately switches a reference capacitor CREF to a reference voltage (ground) and to the inverting signal input of the operational amplifier. The comparator output is connected via a control logic to an inverter INV, and via a reference resistance RREF to the reference capacitor CREF. The reference capacitor CREF is precharged with the corresponding digital output signal in a first clock phase, and transfers a charge packet Q=C·ΔU to the integrator in a second clock phase when the switch S switches the reference capacitor CREF to the inverting input of the operational amplifier. Charge packets of constant charge Q are displaced in the second clock phase, the direction of the charge displacement depending on whether the inverter receives a falling or rising signal edge from the control logic. The recharging of the capacitor CREF is performed with an exponentially falling signal edge whose time constant is τ=RREF×CREF. Because of the falling signal pulse shape, the charge Q displaced by a clock cycle T varies only slightly when clock jitter occurs, and so the linearity of the time-continuous sigma/delta analog-to-digital converter in accordance with FIG. 5 is less sensitive to clock jitter when it occurs than are the analog-to-digital converters illustrated in FIGS. 1 and 2.
FIG. 6 shows a further sigma/delta modulator according to the prior art, which uses a switched capacitor in the feedback branch. Two switches S1, S2 are driven by a switch control logic as a function of the digital output signal of a comparator.
In a first logic state (D=1) of the digital output signal D, the two switches S1, S2 are switched in phase, that is to say the two switches S1, S2 switch the reference capacitor CREF at the same instant to ground (GND) and, in the next clock phase, on the one hand to the inverting signal input of the operational amplifier and to a reference voltage source, which supplies a reference voltage VREF. In the first clock phase when both switches S1, S2 are in the left-hand switch position, the reference capacitor CREF is discharged. In the second clock phase, a charge Q=CREF×Δu=CREF×(Vref−VGND) is displaced to the integrator I.
If the comparator outputs an output data bit D with a low logic value (D=0), the two switches S1, S2 are operated in antiparallel or phase opposition, in a first clock phase the switch S1 connecting the reference capacitor CREF to ground (GND), and the switch S2 connecting the reference capacitor CREF to the voltage source such that the reference capacitor CREF is recharged. Subsequently, in a second clock phase the switch S1 connects the reference capacitor CREF to the integrator I, and the switch S2 connects the reference capacitor CREF to ground (GND), and so the recharged capacitor CREF is discharged via the switch S2, and draws a charge Q=C×Δu from the input of the integrator I. If the logic output data bit D of the comparator is logically high (D=1), a charge packet Q is output to the integrator I in a clock cycle T from in-phase switching of the switches S1, S2. If, vice versa, the data bit D is logically low (D=0), a charge packet Q is drawn from the integrator I in a clock cycle T because of the operation of the switches S1, S2 in phase opposition.
The sigma/delta modulator according to the prior art which are illustrated in FIGS. 5, 6 certainly greatly diminish the sensitivity to clock jitter, but they have the substantial disadvantage that sizeable voltage jumps Δu occur at the signal input of the integrator 5. Consequently, the sigma/delta modulators according to the prior art which are illustrated in FIGS. 5, 6 require operational amplifiers which operate particularly quickly. Such operational amplifiers require a very high supply current, however.